<div class="xbCN0b KiNied M0TuQ" data-announce-callout="true" data-is-announcement-assertive="false" data-liveregiontext="Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Poughkeepsie, NY, USA; Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA." data-use-announcer-service="false" jsaction="rcuQ6b:rcuQ6b;" jscontroller="u3jeub" role="none"><div class="OJgC7b"><div aria-label="Info" class="quEfK" role="img"><i aria-hidden="true" class="google-material-icons notranslate Auu9lc">info_outline</i></div><span aria-hidden="true" class="v7dlUb" jsname="arU4oc">X</span><span aria-live="polite" class="v7dlUb" jsname="yW4uId" role="status"></span><span class="MyVLbf" jsname="MyVLbf">Note: By applying to this position you will have an opportunity to share your preferred working location from the following: <b>Poughkeepsie, NY, USA; Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA</b>.</span></div><span class="GMWBfb NOIZeb" role="none"><span class="gdNP2" jsname="gdNP2" role="none"></span></span></div><br/><h3>Minimum qualifications:</h3><ul>
<li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.<br/></li>
<li>1 year of experience in microprocessor architecture through coursework, academic projects, internships, or industry experience.</li>
<li>Foundational experience in logic design through academic projects, internships, or industry experience.</li>
</ul><br/><h3>Preferred qualifications:</h3><ul>
<li>Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.<br/></li>
<li>Experience with modern processor microarchitecture and related technologies and algorithms, through academic projects or industry experience.</li>
<li>Knowledge of programming languages such as C, C++, and Python.</li>
<li>Knowledge of general purpose operating systems such as Linux or Android.</li>
</ul>
<h3>About the job</h3><p>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.</p>
<p>Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.</p><p>The US base salary range for this full-time position is $113,000-$161,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.</p><div>Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about <a href="#" target="_blank">benefits at Google</a>. </div>
<h3>Responsibilities</h3><ul>
<li>Provide CPU front-end designs, emphasizing on microarchitecture and Register-Transfer Level (RTL) design for the next generation CPU.</li>
<li>Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements and facilitate final decision making.</li>
<li>Deliver designs that meet Power, Performance, and Area (PPA) goals with production quality.</li>
<li>Be familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.</li>
<li>Work closely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals.</li>
</ul>
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also <a href="#" target="_top"> Google's EEO Policy</a>, <a href="#" target="_top">Know your rights: workplace discrimination is illegal</a>, <a href="#" target="_top">Belonging at Google</a>, and <a href="#" target="_top">How we hire</a>.

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. 

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Google

Google is a global technology leader focused on organizing the world's information. We seek a full-time CPU Register Transfer Level Designer with a degree in Electrical/Computer Engineering or related field. You will design CPU front-end microarchitecture and RTL for next-gen silicon. We offer a salary range of $113,000-$161,000 plus bonus, equity, and benefits.

CPU Register Transfer Level Designer

Summary