Standard Job Description

Lockheed Martin Missiles and Fire Control (MFC) is seeking a Senior ASIC & FPGA Design Engineer to join our Programmable Logic Design team. MFC is a recognized designer, developer, and manufacturer of precision engagement aerospace and defense systems for the U.S. and allied militaries. This role offers an excellent working environment with a mix of cutting-edge digital design, hands-on laboratory testing, and product development. You will work with and learn from industry-leading circuit design professionals in a collaborative, mission-driven environment.

What You Will Be Doing

The Senior ASIC & FPGA Design Engineer will serve as a key technical contributor on one or more defense programs, leading the design, verification, and integration of advanced FPGA-based solutions. Responsibilities may include:

• Defining architecture and design specifications for programmable logic components, developing and documenting RTL (VHDL/Verilog/SystemVerilog) that meets performance, power, and reliability requirements

• Creating synthesis, place and route, and timing closure strategies to ensure deterministic operation across target FPGA devices

• Generating comprehensive test plans, simulation models, and verification environments (UVM, SystemC, Python-based testbenches) to validate functional correctness and timing margins

• Leading hardware-in-the-loop (HIL) testing, board-level debugging, and integration with subsystem-level hardware

• Translating system-level performance, safety, and reliability requirements into detailed FPGA architectures

• Conducting timing analysis, power budgeting, and resource utilization studies to optimize device selection and FPGA utilization

• Managing configuration control (GitLab or equivalent), maintaining version-controlled design repositories, and ensuring traceability of all artifacts

• Producing comprehensive design documentation, including specifications, test plans, verification reports, and release packages compliant with aerospace standards

• Collaborating with cross-functional teams — systems, software, hardware, mechanical, test, manufacturing, and quality — to ensure seamless integration and compliance with program milestones

• Providing technical mentorship to junior engineers and promoting best practices in FPGA development, verification, and configuration management

This position offers the opportunity to work alongside experienced ASIC & FPGA design professionals and gain exposure to cutting-edge defense technology.

Candidates may be subject to a government security investigation and must meet eligibility requirements for access to classified information.

Basic Qualifications

• Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master’s degree preferred

• Minimum 3 years of professional experience with FPGA design and simulation verification or a related discipline

• Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog

• Experience with Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and UltraScale design methodology

• Experience with FPGA simulation tools such as Synopsys VCS

• Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity

• Experience with high-speed interfaces such as AXI, Ethernet, TCP/IP, PCIe, and serial protocols

• Practical laboratory debug experience with high-speed oscilloscopes, spectrum analyzers, and signal generators

• Familiarity with Synopsys EDA tools

• Must be a US Citizen; must possess a DoD Secret clearance

Desired Skills

• LM/MFC design experience and missile program experience

• Experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets

• Experience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric and IP

• Experience implementing NSA algorithms (e.g., AES, counter mode)

• Experience managing configuration control (GitLab preferred)

• Experience with Vivado and Vitis FPGA toolsets

• Experience with UVM and Simulink/HDL Coder integration

• Comfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators, and other test equipment

• Experience with troubleshooting and debugging at board level, including FPGA validation

• Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)

• Strong communication, collaboration, and presentation abilities

• Controls and digital loop-closure application knowledge

• Networking proficiency with Ethernet switches, routers, firewalls, and debugging tools (tcpdump, Wireshark)

• Active DoD Top Secret clearance

Pay Information

Full-Time Salary Range: $98100.00 - $182100.00

At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow—both professionally and personally.

The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer.

Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.

• Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.

• For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.