Your Role

車載向けMCUの物理設計エンジニアとして設計環境の構築改善から物理的実装までをご担当いただきます。

Key responsibilities in your new role

• Responsible for planning and execution of all aspects of Physical Design Implementation including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification using EDA tool chain (FusionCompiler) w/ the low power design.

• Responsible for planning and execution of Timing Related Checks which include Timing Fixture, Hold & Setup Requirement, DRV checks, Power Intent spec and checks and all Signoff Checks

• Support the schedule and plan arrangements to meet project milestones deadlines, aligning w/ the other cluster designer, reporting regularly to project manager the status of the entire layout development.

• The candidate should have reasonable ability to automate design work by means of script programming, e.g. Tcl/tk and Python.

Your Profile

Qualifications and skills to help you succeed

• 3+ years of hands-on experience in Floorplanning, Place and Route, Clock tree synthesis, Physical Verification error fixing and logic synthesis

• Understanding of timing constraints, Static Timing Analysis and timing sign-off conditions

• Understanding of IREM flow and Multiple power domain design flow.

• Deep understanding of scripting languages (shell, perl, tcl and Physon) and Make flow

• Drive ambitious schedules and enables dependent teams to accomplish.

• Should be self-motivated and take initiatives to drive new methodologies

• Team Worker

• Language : Business Japanese, Business English

• Basic PC Skill (MS Office)

• Bachelor degree or above in Digital Design or any relevant field

※応募時には日本語の履歴書・職務経歴書・英文のレジュメの3点をご提出ください

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