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About this opportunity:

Power is a first-order design constraint in modern SoC ASIC IPs, yet actionable power feedback traditionally arrives late in the design cycle. For IP teams that need to handle power analysis and optimization goals this can be costly as RTL and microarchitectural decisions are locked in long before their power impact becomes visible, and every iteration carries the runtime and complexity overhead of a full implementation pass plus gate level simulations (GLS). Early RTL power analysis is not a sign-off activity, i.e. absolute accuracy is not the main goal and what matters is understanding power trends, catching power bugs, and extracting meaningful metrics on the profile of a still-evolving IP. Additionally tracking RTL-level optimizations over time, and cross-probing results back to RTL for actionable debug is of big value. A "shift-left" methodology targets exactly this need by producing physically-credible power estimates directly from RTL, fast enough to fit an iterative workflow.

This thesis aims to evaluate such a flow based on Synopsys RTLA and PrimePower RTL (PPRTL2.0), applying post-synthesis/PnR-derived settings through physical-aware synthesis to generate a pseudo-netlist and deliver fast-turnaround power analysis without a full backend pass or GLS. This evaluation is to be done in a production silicon context using existing established flows as reference and for key EMCA IPs like the Common Memory Subsystem, DSP, hardware accelerators (HWAs), HW Job/Resource Manager, and AMBA Bridge.

What you will do:

Evaluate the RTLA/PPRTL2.0 hybrid and logical flows as a shift-left RTL power analysis methodology aimed at early insight by assessing:

• Relative accuracy and trend fidelity versus a full netlist-based flow — i.e. does the flow rank alternatives and track deltas correctly, even if absolute numbers differ.

• Runtime reduction from avoiding full implementation and GLS, enabling frequent iteration.

  • complexity reduction, particularly GLS avoidance.

• Fidelity for glitch power (via Delay-Shifted Analysis), the ability to track the power impact of RTL/datapath changes and optimizations.

• The quality of metrics extraction and RTL cross-probing for power-bug hunting on an in-progress IP.

• Vector-based and vectorless analysis, including metrics extraction and vectorless flow characterization with recommendations and identified limitations.

• RTLA pseudo-netlist to real (Fusion Compiler) netlist alignment — how well the physical-aware synthesis topology tracks the implemented netlist, since this underpins trust in the trends.

Deliver a documented, reproducible methodology and flow setup for RTLA/PPRTL 2.0 (hybrid+logical), oriented toward frequent early-RTL use.

The skills you bring:

• Master´s student in Electrical/Computer Engineering, Computer Science or similar.

• Background in ASIC design, RTL HDL coding, testbench design using SystemVerilog, working knowledge of UVM, and scripting (Tcl/Python) for EDA tools is preferred.

Why join Ericsson?

At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: Sweden (SE) || Stockholm

Req ID: 791066