Master Thesis: Advanced IP Netlist Power Regression and AI-Ready Analytics Framework

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About this opportunity:

In an outsourced ASIC backend model, the in-house middle-end team owns the prelayout netlist generation and hands official netlist drops to an external vendor at defined IP design drop points. In-house power analysis needs to track every drop against the real netlist that actually goes out. Yet today this is largely manual, inconsistent across IPs, and disconnected from the vendor's postlayout reality. RTL power tools, such as SpyGlass-Power, provide rich shift-left dashboards and metrics but operate before synthesis on pseudo-netlist. The gap is a flow that retains this rich analytics visibility while working on the real netlist: automatically regressing power on each drop, feeding vendor GLS collaterals, and producing a structured, AI-ready dataset that makes residual/redundant-power interpretation fast and actionable.

The aim of this thesis is to realize and pilot an automated, AI-ready post-processing and interpretation framework for IP-level netlist power analysis and optimization, triggered on every official netlist drop, minimizing intra- and inter-organization friction across the frontend/vendor handoff. By automating regression, method dispatch, and result interpretation, the framework turns power analysis into an early, repeatable, and conclusive activity.

What you will do:

Build a drop-triggered power regression that selects the method per IP: GLS-based for key IPs, vectorless for the rest, with the framework able to produce all the metrics that drive the vectorless flow.

• For key IPs, generate and validate GLS collateral (replay testbenches, sanity checks) so the vendor can correctly replay GLS on their postlayout netlist.

• Deliver an in-house analytics layer that ingests FusionCompiler and PTPX/PrimePower prelayout results and presents them as interactive, hierarchical treemaps across power groups and submodules, annotated with switching activity and clock-gating efficiency (dCGE) and other FC QoR metrics.

• Implement an AI-ready interpretation layer over the structured dataset (PTPX reports → normalized schema / Parquet artifacts), delivered at two capability tiers:

  • Tier 1 (core): natural-language questions are translated into deterministic queries over the columnar dataset — retrieval, filtering, ranking, and threshold reports (e.g. registers below the dCGE threshold, dominant residual-power scopes).
  • Tier 2 (assistive): correlation and hypothesis generation — clustering offenders by hierarchical parent, cross-probing residual activity to source, surfacing glitch hotspots and connection to the datapath QoR reports, and proposing operating point-aware optimization opportunities as engineer-confirmable suggestions. Focus adapts to the operating point: clock-gating and datapath residual power at idle; glitch sources and gating efficiency (e.g. ROADF) in active windows.

• HTML dashboard that presents the analysis results for shared, low-friction access—rendering hierarchical treemaps (power/DCGE by module), pie charts (power-group breakdowns), and trend lines that track metrics across successive netlist drops so regressions are visible drop-over-drop.

The skills you bring:

• Master´s student in Electrical/Computer Engineering, Computer Science or similar.

• Background in Computer architecture, ASIC design, RTL HDL coding, testbench design using SystemVerilog, working knowledge of UVM, and scripting (Tcl/Python) for EDA tools is preferred.

Why join Ericsson?

At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: Sweden (SE) || Stockholm

Req ID: 791067