Mid-Level, Senior
SRAM Memory Design
Position Summary
Position: SRAM Memory Design Engineer:
Roles and Responsibilities:
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Design highly competitive circuits to meet performance/power specifications requested by customers
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Guide and lead a group of engineers to deliver the SRAM IP in the given timelines
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Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design.
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Own the responsibility from SPEC to GDS and DK delivery.
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Review circuits, robustness reports and identify potential robustness issues.
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Review Layouts and suggest improvement areas to achieve competitive PPA
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Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC
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Must be able to communicate effectively across different teams.
Role and Responsibilities
Skills & Experience:
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Master/Bachelor in electronics
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Working experience in preferably Memory design
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Understanding of RC network and FINFET fundamentals are necessary.
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Custom or Compiler SRAM/ROM development experience
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Fundamentals of process variability and its effect on memory design
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Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM)
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Strong understanding of circuit design fundamentals
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Critical path modelling concept, various type of models ( RC, C, Pai,ladder)
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Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitic etc
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Analysing layout and understanding of LLE effects.
Skills and Qualifications
Experience – 4 to 10 Years of experience
Qualifications: B.Tech/B.E/M.Tech/M.E
Disclaimer: Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law
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