SoC DFX Staff Engineer

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THE ROLE: We are seeking an experienced SoC DFX Engineer to help define, design, and verify robust Design for Test (DFT) and Design for Debug (DFD) solutions for complex, high‑performance SoCs. In this role, you will collaborate closely with architecture, RTL, firmware, and verification teams to integrate DFX features that enable efficient silicon validation, bring‑up, and debug across the full product lifecycle. This position offers hands‑on technical depth, system‑level problem solving, and the opportunity to influence DFX strategy in advanced processor designs.

THE PERSON: You are a curious and driven engineer with a strong interest in complex processor architectures and system‑level problem solving. You bring a collaborative mindset and communicate clearly and professionally, enabling you to work effectively with cross‑functional teams distributed across sites and time zones. You are proactive, adaptable, and comfortable navigating ambiguity, with the ability to break down complex technical challenges and drive them to resolution. You take ownership of your work, value constructive feedback, and are eager to learn, continuously improve, and contribute to both technical excellence and a positive team culture.

KEY RESPONSIBILITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new DFX features to be designed and verified.

• Work on designing and integrating DFX logic in complex SoCs.

• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases

• Estimate the time required to write the new feature tests and any required changes to the test environment

• Build the directed and random verification tests

• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

• Experience with DFT (Design for Test) and DFD (Design for Debug) architecture, design, and verification

• Experience with JTAG, LBIST, MBIST, Scan, and ATPG

• Familiarity with the Tessent tools suite, including Scan and ATPG

• Familiarity with test pattern generation, bring‑up, and debug on ATE

• Experience with post‑silicon bring‑up

• Experience with IP‑level and ASIC verification

• Experience debugging firmware and RTL code using simulation tools

• Experience with Verilog, SystemVerilog, SystemC, and C++

• Experience automating workflows in a distributed compute environment

• Experience with UVM concepts and the SystemVerilog language

• Experience with static timing analysis and constraints

• Familiarity with ICL/PDL

• Scripting language experience: Perl, Ruby, Makefile, and shell preferred

• Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

LOCATIONS:

• Markham, Vancouver, Ottawa, Calgary

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Benefits offered are described: AMD benefits at a glance

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.